To save die space in latch-based arrays, it is known to use a master latch that drives a data output in parallel to a column of slave latches. For example, FIG. 1 illustrates a column 101 for a latch-based array 100. Column 101 includes a single master latch 105 that drives a master-latched data output 102 in parallel to four slave latches 110. For each column 101, slave latches 110 correspond to the various rows, ranging from a slave latch in row 0 to a slave latch in row 1 The master and slave latches are driven by a clock signal 135, which is gated for the rows during a write operation so that it is asserted to only an active row of slaves (the row being written to or read from). Clock signal 135 is thus equivalent to a word line signal for slave latches 110 in that an entire row of slaves is activated at a time by clock signal 135. Clock signal 135 is gated to all the remaining rows during the activation of a particular row.
Master latch 105 is always clocked during a write operation regardless of which row is selected for the write operation. For example, master latch 105 may be an active low latch whereas slave latches 110 may be active high latches. As clock signal 135 goes low, master latch 105 latches an input data signal 103 to form master-latched data output 102. As clock signal 135 goes high for the selected row (the row receiving the non-gated clock signal 135), the corresponding slave latch 110 in the selected row latches master-latched data output 102. In this fashion, when a particular row's clock signal 135 is activated (not gated), master latch 105 and the slave latch 110 for the selected row form a rising-edge-triggered flip-flop combination that latches master-latched data output 102 in a write operation. If master-latched data output 102 wasn't shared by the column's slave latches, there would need to be three more master latches in column 101 such that each row/column intersection would have its own master/slave flip-flop pair. In contrast, the shared master architecture in column 101 needs only a single master latch 105. The data outputs from the slave latches 110 for each row in column 101 range from a data output IW0 for row 0 to a data output IW3 for row 3. A 4:1 output multiplexer 115 selects from these row data outputs IW0 through IW3 to provide a column data output 117 responsive to decoding two address bits A0 and A1.
To save die space, it is conventional to implement output multiplexer 115 with a two-to-four decoder 120 and an associated collection of logic gates. Two-to-four decoder 120 is configured to produce four read enable signals RE0, RE1, RE2, and RE3 responsive to decoding the two address bits A0 and A1. Only one read enable signal is asserted in any given read operation. For example, if RE0 is asserted to a logical one value, the remaining read enable signals RE1, RE2, and RE3 all de-asserted (equaling logical zero values in an active high embodiment).
Each row's data output and read enable signal are processed by a corresponding AND gate. For example, an AND gate 125 processes IW0 and RE0 for row 0, an AND gate 130 processes IW1 and RE1 for row 1, and an AND gate 140 processes IW2 and RE2 for row 2. Finally, an AND gate 145 processes IW3 and RE3 for row 3. An OR gate 150 ORs the outputs from the AND gates to provide column data output 117 responsive to the asserted read enable signal. Based upon the address signals A0 and A1, decoder 120 asserts only one of the read enable signals in any given read operation. Although instantiating 4:1 output multiplexer 115 in this fashion is advantageous with regard to saving die space, the resulting fault testing of the read enable signals such as RE0 through RE3 is problematic as discussed further below.
Read enable fault testing determines whether a read enable signal has a stuck-at-one fault or a stuck-at-zero fault. For example, suppose one wants to test whether a stuck-at-one fault exists for read enable signal RE0. If read enable signal RE0 were stuck at a logical one value, the row 0 data output IW0 will always pass through AND gate 125 regardless of whether another row's read enable signal is being asserted. It is thus important to isolate and identify stuck-at-zero (and stuck-at-one) faults for the read enable signals in a column of slave latches that are all driven in parallel by a master latch. But the isolation of such faults requires complex sequential automated test pattern generation (ATPG) testing to decorrelate a column's slave latches.
Accordingly, there is a need in the art for master/slave latch-based memory arrays having enhanced fault testing for the read enable signals.